Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and the like.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and the like.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory (e.g., FLASH memory). In other CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory (e.g., static memory cells) as part of an initial configuration sequence.
PLDs are typically controlled by an instruction set. On CPLDs, these instructions are typically IEEE 1149.1 (Joint Test Action Group (JTAG)) or IEEE 1532 (In-System Configurable (ISC)) compliant instructions. On FPGAs, instructions can be either JTAG/ISC compliant instructions or configuration bitstream instructions. The instructions for PLDs are used both for testing the device and its board connections, as well as for reading, writing, and erasing the volatile and/or non-volatile memories on the chip.
In some cases, it is desirable to include security features for controlling access to the volatile and/or non-volatile memories on a PLD. One proposed solution is to provide the ability to completely disable the boundary scan port on the PLD to prevent the PLD from receiving any instructions. While such boundary scan blocking reduces the potential for a hacker to reverse engineer a design in a PLD, such blocking has the disadvantage of relinquishing boundary scan compliance for the sake of security. Accordingly, there exists a need in the art for an improved method and apparatus for providing secure programmable logic devices.